This thesis presents an overview of my published work on streamlining and optimizing quantum processors. Complete, microscopic, quantum-gate–by–quantum-gate simulations of a variety of quantum circuits are implemented and executed on state-of-the-art multi-processor parallel computers. A host of analytical scaling formulas addressing the quality of quantum processors, e.g., in the presence of realistic gate errors and defects, are presented. These formulas reliably describe the practically interesting, large-number-of-qubit regime, inaccessible to simulations on classical computers. Much of the technical details may be found in my published articles, which appear in the Appendix. This thesis also presents the generic and specific directions into which my current investigations are headed. In addition, several preliminary results are presented and discussed.
Nam, Yunseong, "Robustness and Performance Scaling of Large-Scale Quantum Computers with Faulty Gates" (2016). Dissertations. 62.
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